The designers of many devices that incorporate semiconductors desire integrated circuits that have large tuning ratios of accumulation to inversion. Semiconductor devices, such as integrated circuits, may include varactors which have a capacitance element that is dependent on the applied voltage. The varactors generally rely on large capacitance differences between Vg=0V and Vg>Vt to provide a tunable capacitance. Currently available FinFET devices are fully depleted devices that include depletion region widths that are limited by the width of the device fins and the current FinFET devices and fabrication methods do not enable a designer to alter the fin width. The gate capacitance swing from Vg=0V to Vg>Vt, in the currently available FinFET devices, is very small because the fin widths are small. The fin widths in FinFET devices also result in the fins being generally fully depleted at Vg=0V.
Thus, the currently available FinFET devices do not have large tuning ratios and design and fabrication methods are needed to form FinFET devices with larger fin widths to improve electrical performance of the resultant semiconductor devices by forming a higher tunability FinFET varactor.